1. Field
This disclosure relates generally to a flip-flop and, more specifically, to a pulsed state retention power gating flip-flop.
2. Related Art
State retention power gating (SRPG) is a technique employed in flip-flops to reduce static leakage current by powering down certain components of the flip-flop during periods of inactivity. Reducing power consumption of electronic devices during periods of inactivity is commonly employed in battery-powered devices, such as mobile telephone handsets. Conventional SRPG flip-flop configurations have saved a logic state (‘0’ or ‘1’) of an SRPG flip-flop in a retention latch prior to power-down. A common flip-flop configuration is a master-slave configuration in which a master latch feeds a slave latch. At least one conventional SRPG flip-flop configuration has maintained power to the slave latch (to preserve a current logic state) when other components of the SRPG flip-flop, including the master latch, are power-gated (i.e., power is removed from the master latch and other components). In general, the slave latch (which has acted as a retention latch and has remain powered during a power-down condition) has consumed a non-significant amount of static leakage current in the power-down state.
U.S. Pat. No. 7,164,301 (hereinafter “the '301 patent”) discloses an imbalanced state retention power gating (SRPG) flip-flop that forces a known state upon power-up, depending upon the state being stored, to save additional static leakage current. More specifically, the '301 patent discloses removing power from a slave latch (in addition to an associated master latch) that is in a predetermined state prior to power-down to save additional static leakage current in the power-down state.
With reference to FIG. 1, a conventional non-pulsed SRPG flip-flop 100 is illustrated. The flip-flop 100 includes a retention latch 130, which includes inverters 102 and 104 and pass gates 106 and 108. First terminals of the pass gates 106 and 108 are coupled to an input of the inverter 102 and second terminals of the pass gates 106 and 108 are coupled to an output of the inverter 104. An output of the inverter 102 is coupled to an input of the inverter 104. The pass gate 108 is turned on when a clock (CPN) signal (which is an inverted version of a clock (CPI) signal) is in a high logic state and the pass gate 106 is turned on when a power-down (PD) signal is in a high logic state, i.e., when the flip-flop 100 is not in a deep sleep (power-down) mode. A first input of an inverting multiplexer 120 is configured to receive a data (D) signal and a second input of the multiplexer 120 is configured to receive a test input (TI) signal. A control input of the multiplexer 120 is configured to receive a test enable (TE) signal that, when asserted, selects the TI signal such that a scan function may be performed. An output of the multiplexer 120 is coupled to a first terminal of pass gate 118, which is turned on when the CPN signal is in a high logic state. A second terminal of the pass gate 118 is coupled to an input of inverter 116 and a first terminal of pass gate 114, which is turned on when the CPI signal is in a high logic state.
A second terminal of the pass gate 114 is coupled to an output of an inverter 112, whose input is coupled to an output of the inverter 116. An input of inverter 122 is coupled to the output of the inverter 116 and the input of the inverter 112. A functional latch 140 is formed by the inverters 112 and 116 and the pass gate 114. An output of the inverter 122 is coupled to a first terminal of a pass gate 124, which is turned on when the CPI signal is in a high logic state. A second terminal of the pass gate 124 is coupled to a drain of n-channel metal-oxide semiconductor field-effect transistor (MOSFET) 128, an input of an inverter 126, and a first terminal of pass gate 110, which is turned on when the PDN signal is in a high logic state. A second terminal of the pass gate 110 is coupled to an input of the inverter 102. In general, the flip-flop 100 has a relatively high CPI pulse high time requirement. Moreover, the flip-flop 100 requires the maintenance of multiple signals (i.e., the CPN and PDN signals) when the flip-flop 100 is in a power-down mode, requires that the CPN signal be in a certain state when entering and exiting the power-down mode, and employs a relatively large number of devices in a speed path (data input (D) to data output (Q) path) which causes the flip-flop 100 to have a relatively high propagation delay.
In general, pulsed SRPG flip-flops are designed to reduce a speed path delay by reducing the number of components in the speed path of a flip-flop. For example, U.S. Patent Application Publication No. 2006/0197571 (hereinafter “the '571 application”) discloses a multi-threshold complementary metal-oxide semiconductor (MTCMOS) pulsed SRPG flip-flop that includes a scan function that is input into a retention latch of the flip-flop to, apparently, reduce the number of components in the speed path of the flip-flop. As is known, an MTCMOS circuit usually employs low threshold voltage (general power (GP)) CMOS transistors to implement a desired function during normal operation (power-up) mode and high threshold voltage (low power (LP)) CMOS transistors to reduce leakage current during a sleep (power-down) mode. In general, the pulsed SRPG flip-flops disclosed in the '571 application have a relatively high leakage current when in a power-down mode, require the maintenance of multiple signals when in a power-down mode, and require that a clock signal be in a high logic state when going into power-down in order to save a current state of the flip-flop in a retention latch.
What is needed is a pulsed state retention power gating flip-flop that exhibits lower leakage currents when in a power-down state.